koulib@sh.itjust.works to Linux@lemmy.mlEnglish · 5 days agoWhich new Protocol or Standard are you most excited about?message-squaremessage-square52fedilinkarrow-up189arrow-down13file-text
arrow-up186arrow-down1message-squareWhich new Protocol or Standard are you most excited about?koulib@sh.itjust.works to Linux@lemmy.mlEnglish · 5 days agomessage-square52fedilinkfile-text
minus-squaresecret300@lemmy.sdf.orglinkfedilinkarrow-up153·5 days agoRISC-V I want open-source hardware
minus-squarepizzaboi@lemm.eelinkfedilinkEnglisharrow-up22·5 days agoIs there a good resource out there for wrapping my head around RISC-V? Last time I read a wiki my head hurt haha. Seems cool, though.
minus-squaredeur@feddit.nllinkfedilinkarrow-up21·edit-25 days agoIn principle it’s just "slimmer ARM!. RISC-V is also extremely dedicated to using memory mapped IO rather than older style IO x86_64 supports. Think lots of registers, a fun zero register that is always zero, and memory mapped IO.
minus-squaremvirts@lemmy.worldlinkfedilinkarrow-up5·4 days agoI for one think we need a register for each unsigned integer, why is zero so special? :P Or if we can’t get that, at least every power of 2 and power of 2 minus 1. Maybe I can submit a proposal for risc-VI 🤣
minus-squarePetteriPano@lemmy.worldlinkfedilinkarrow-up9·4 days ago Maybe I can submit a proposal for risc-VI 🤣 No need! You can make your own custom extension! If the silicon doesn’t support it, then you can provide firmware to emulate it.
minus-squareporl@lemmy.worldlinkfedilinkEnglisharrow-up5·4 days agoI think a register for each of the primes should be enough.
minus-squarecaseyweederman@lemmy.calinkfedilinkarrow-up3·4 days agoARM is also reduced-instruction set but I don’t know how they differ. Is the instruction set somehow more reduced?
minus-squareMonkderVierte@lemmy.mllinkfedilinkarrow-up3·4 days agoAren’t they more like a hybrid instruction set and architecture?
minus-square☆ Yσɠƚԋσʂ ☆@lemmy.mllinkfedilinkarrow-up7·edit-24 days agosome good news on that front https://github.com/OpenXiangShan/XiangShan
minus-squareMwa@lemm.eelinkfedilinkEnglisharrow-up1arrow-down4·edit-23 days agoImma stick with ARM and x64 ngl, ik it’s not open hardware but I don’t really mind that but cool to hear.
RISC-V
I want open-source hardware
Is there a good resource out there for wrapping my head around RISC-V? Last time I read a wiki my head hurt haha. Seems cool, though.
In principle it’s just "slimmer ARM!. RISC-V is also extremely dedicated to using memory mapped IO rather than older style IO x86_64 supports.
Think lots of registers, a fun zero register that is always zero, and memory mapped IO.
I for one think we need a register for each unsigned integer, why is zero so special? :P
Or if we can’t get that, at least every power of 2 and power of 2 minus 1.
Maybe I can submit a proposal for risc-VI 🤣
No need! You can make your own custom extension! If the silicon doesn’t support it, then you can provide firmware to emulate it.
I think a register for each of the primes should be enough.
ARM is also reduced-instruction set but I don’t know how they differ. Is the instruction set somehow more reduced?
Aren’t they more like a hybrid instruction set and architecture?
some good news on that front https://github.com/OpenXiangShan/XiangShan
Imma stick with ARM and x64 ngl, ik it’s not open hardware but I don’t really mind that but cool to hear.