Sorry about that, I should have spelled out RTL as Register Transfer Level in the paper. But yeah given the references to Verilog and hardware design it can be deducted…
- 0 Posts
- 2 Comments
Joined 2 年前
Cake day: 2023年9月30日
You are not logged in. If you use a Fediverse account that is able to follow users, you can follow this user.
In the paper, RTL stands for Register Transfer Level, in the domain of digital circuit design -> https://en.wikipedia.org/wiki/Register-transfer_level