

Props for the detailled answer, but this all sounds completely backwards.
Low-side switching should in general use an N-Channel FET. And with your voltage divider, the gate will be at 9% of the supply voltage, not 91%, which means the FET will always be conducting. It will also never fully turn on, because that would mean the Gate-Source voltage would drop to near 0, which would turn it off again - it will instead settle somewhere near the GS threshold voltage from Drain (and Gate) to Source. Moreover, PMOS devices are not controlled by the Gate-Drain voltage, but with the Gate-Source voltage, just like NMOS devices.
My counter proposal:

Edit: Note that this is an N-Channel FET
Edit 2: Changed image, I initially placed the resistor and the tripwire the wrong way around.






With a PMOS device used for simple on/off switching, placing the load between drain and ground would be correct. With an NMOS FET, the load should be between drain and VCC.
In general: NMOS source to GND, PMOS source to VCC.