I’ll also jump in, mirroring some of what jeinzi said, and providing some of my own thoughts. I agree that both what you originally had, and what you have now should work.

Your schematic should read left-to-right with the flow of current. I don’t believe a wire is necessary, though I do see how it could be beneficial. The only thing I would change is flipping Q1 so that VOUT is on the right side of the schematic instead of being on the left as it is now. I had to do a double take to figure out what was going on there.

I also tend to prefer global labels, especially with a single page schematic like this, as they’re a little easier to read than the standard net labels.

On to layout, I’m a “Route Power, pour ground everywhere else” kinda guy. Remove islands, but I then via stitch all my grounds together. This is most useful for higher layer count boards and stuff dealing with RF. This shouldn’t see any of that, so it’s less of an issue. I rather dislike the setup with the 5 separate planes/pours on this board. I forked your repo and quickly threw together how I personally would route it, assuming I:

• Couldn’t use different components (0603 or really 0402 for the passives) (different PMOS package)
• Couldn’t change the outline (Okay, I lied here. Please round your corners. Right click -> shape modification -> fillet [or chamfer]. Makes the board feel so much more premium, and gets rid of those awful sharp corners.)
• Couldn’t change the placements of the USB Connector and Terminal block.

Hopefully that’s somewhat useful and doesn’t feel like I’m stomping on toes.

Some additional ancient knowledge. Try to avoid sharp angles when laying out traces. I see that you’ve got a lot of those, especially near the jumpers. The old wisdom is that acid from the etch can get stuck in the corner and slowly eat away at the trace. The honest reality is that this is not a problem anymore, but it is still generally recommended to avoid sharp corners. Especially when you’ve got the space to do so.

Re assembly. I think this is all doable by hand with a nice soldering iron and maybe a light pair of hobby magnifiers at worst. I strongly prefer “bevel” style tips. TS-BC2 for TS100/pinecil. You could also go with solder paste and either a hot air gun or a hot plate. If you get low melt solder paste (138C), you can even use an old clothing iron if you’ve got a way to hold it upright.

This is really scattered, so let me know if you’ve got any questions or if there’s anything I missed.

tl;dr: I’m reasonably sure this will work as is.

The following comments involving my personal opinions might be most useful for more complex projects:

While I also try to isolate building blocks in my schematics, I think it’s sometimes beneficial to have some visible connections using wires. Your schematic isn’t very complex, but I still needed to jump around a bit to understand how current flows from the USB connection to the output. I would arrange the building blocks so that current flows from left to right and include one wire that starts at the USB jack, passes by the CH224K and its bypass cap, through the FET to the terminal block, so you can read the current flow like you would a line of text.

Layout:

• Before manufacturing, better before starting the layout, I would include the design rules of your manufacturer under File > Board Setup > Design Rules > Constraints. Currently you haven’t defined minimal clearances, widths etc. Google “[your preferred manufacturer] capabilities”. You might also find existing KiCad templates that you can import.
• I would place the reference designators on the silkscreen so they are visible after assembly, to help with debugging and repairability.
• I would also take care that everything you want to show is legible; currently, your JP-labels overlap U1
• To find enough room on the silkscreen, you could probably reduce your text size. Look up the minimum in your manufacturer capabilities; in addition to putting those values into your design rules, you can also add them in File > Board Setup > Text & Graphics > Defaults > Silk Layers. Apart from that being the new standard, you can then also easily go to Edit > Edit Text & Graphics Properties to set all existing reference designators to those new default values. In my personal experience (with JLCPCB at least), the text also stays legible waayyy below the quoted minimum size.
• I make it a point to include some metadata on all my PCBs; a version number, date, a project title and the name of the designer, so I don’t confuse myself or others when the PCB is found some years later in a random box.
• I like your package size for the resistors and caps, but if you have space issues, you will probably have no issue soldering the smaller 0805 packages by hand either. We regularly have discussions what size can be comfortably soldered by hand without magnification; one of my colleagues insists that even 0603 is “comfortable”.
• EDIT: Your trace from the capacitor to the VDD pin of the IC is a bit long. It will work, but it would be better to place the capacitor as close to the IC as physically possible, so that the area enclosed by the loop “Cap.+ -> IC.VDD -> IC.GND -> Cap.GND -> Cap.+” is minimized. Something like this:

Regarding both the schematic and layout: run the ERC/DRC and fix all errors and warnings. Most of it is noise, but hidden beneath that, serious issues can hide. Be sure that you don’t miss anything important there.

Another idea that might be out of scope for your project: You could add optional 5.1k pull-down resistors on the CC lines and a solder jumper from VBUS to VOUT. Then you could use the board even without the CH224K and the FET if you only need 5V.